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FPGA down converter designer
Describe the rates and bands. Get a digital down converter built for FPGA or ASIC use.
FPGA down converter designer is a free AI skill for the job "Build and ship software". Give the instructions to an AI assistant that supports the required files and tools, then review its output.
Free · No account · BSD 2 Clause licence · Made by MathWorks · Level: expert · Thinking: high
Made by MathWorks. See the original on GitHub; we copied it as it is, with its licence.
What it does
A digital down converter that takes a radio signal to baseband, built in MATLAB and ready for FPGA or ASIC code generation. It covers both whole-number and fractional sample rate changes. The chain is an oscillator, a mixer, a CIC decimator and a compensating FIR filter. For fractional rates it adds a Farrow stage. The skill follows firm rules, such as the exact phase increment formula for the oscillator and a single fixed-point multiply for the mixer with no conjugate. It simulates the design against a floating-point reference, then produces Verilog or VHDL. You need MATLAB with the DSP HDL Toolbox.
You give it
- Input sample rate
- Carrier frequency
- Target output rate
- Bandwidth and filter needs
- Word lengths (optional)
You get
- MATLAB model of the converter
- Filter and oscillator settings
- Simulation against a reference
- Verilog or VHDL output
- Notes on design rules followed
Use it when
- You are building a radio receiver front end for an FPGA.
- Your output rate does not divide evenly into the input rate.
- You have a floating-point down converter and need an HDL version.
- You need a CIC and FIR filter chain with sensible word lengths.
How to use it
- Add it to your AI once: download it and add the folder to Claude, ChatGPT or Codex as a skill.
- Ask for the job in your own words. Your AI opens the skill when it fits.
- It works best when your AI can run MATLAB with DSP HDL Toolbox.